Various proposals have recently been made on signal reading performed by a CMOS image sensor. In general, CMOS image sensors based on column-parallel outputting, configured to select pixels of one line out of a pixel array and simultaneously read signals from those pixels in a column direction, are widely employed.
An example of such CMOS image sensors disclosed in Patent Document 1 will be described referring to FIG. 17. FIG. 17 is a schematic diagram showing a configuration of a conventional CMOS solid-state imaging device (CMOS image sensor) 1 in which an AD conversion circuit and a pixel portion are mounted on the same semiconductor substrate.
As shown in FIG. 17, the solid-state imaging device 1 includes a pixel array (imaging unit) 10 including a plurality of unit pixels 3 arranged in a matrix pattern, a drive control unit 7 provided outside the pixel array 10, a column processing unit 26, and an output circuit 28. The column processing unit 26 includes column AD circuits 25 respectively provided for each of vertical columns.
The column AD circuits 25 each include an AD conversion unit (ADC) 251 that converts a pixel signal into digital data, and a data storage unit (memory) 256 that stores the digital data.
The drive control unit 7 includes a horizontal scanning unit 12 that controls column addresses and column scanning circuits, a vertical scanning unit 14 that controls row addresses and row scanning circuits, and a communication timing control unit 20 that generates internal clocks on the basis of a master clock CLK0 received from outside to thereby control the horizontal scanning unit 12 and the vertical scanning unit 14.
Each of the unit pixels 3 is connected to a row control line 15 controlled by the vertical scanning unit 14 and a vertical signal line 19 through which the pixel signal is transmitted to the column processing unit 26.
In the solid-state imaging device 1 thus configured, the pixel signal outputted from the unit pixel 3 of each vertical column is provided to the column AD circuit 25 of the column processing unit 26 through the vertical signal line 19.
The column AD circuits 25 each include a data storage unit 256 that serves as a memory of N bits for storing a counting result retained by the AD conversion unit 251, the data storage unit 256 being located posterior to the AD conversion unit 251.
In addition, the column AD circuits 25 each include a data switching unit (SEL) 258 that switches the data inputted to the data storage unit 256.
The data switching units 258 receive a memory transfer command pulse, which is a controlling pulse common to all the data switching units 258, from the communication timing control unit 20 at a predetermined timing.
Upon receipt of the memory transfer command pulse, the data switching unit 258 transfers data outputted from the corresponding AD conversion unit 251 of the same column to the data storage unit 256. The data storage unit 256 retains and stores the transferred data.
Here, the data switching unit 258 not only transfers the data outputted from the AD conversion unit 251 of the same column to the data storage unit 256, but also transfers data stored in the data storage unit 256 of another column to the data storage unit 256 of the same column.
The horizontal scanning unit 12 serves as a read scanning unit that reads data stored in the data storage units 256 while the AD conversion unit 251 is performing the assigned function.
The output terminal of the data storage unit 256 is connected to a horizontal signal line 18. The horizontal signal line 18 has a width corresponding to N bits which is the bit width of the column AD circuit 25, and is connected to the output circuit 28. The output circuit 28 includes n pieces of sense circuits respectively corresponding to the output lines (not shown).
In particular, the device including the data storage unit 256 configured as above is capable of transferring AD conversion data retained by the AD conversion unit 251 to the data storage unit 256. Accordingly, the device is capable of independently controlling the AD conversion process of the AD conversion unit 251 and the reading of the result of AD conversion into the horizontal signal line 18. Therefore, the device can perform a pipeline operation in which the AD conversion and the signal reading to outside are performed in parallel.
For example, in the case where the column AD circuit 25 is configured to perform AD conversion based on single slope integration, the column AD circuit 25 reads out a pixel signal from the pixel array 10 at a predetermined timing in a horizontal period, and performs the AD conversion based on single slope integration with the pixel signal read out to thereby output a result of the AD conversion at a predetermined timing. In this process, first a voltage comparator included in the AD conversion unit 251 compares a reference signal for comparison (substantially for the AD conversion process) with the pixel signal inputted through the vertical signal line 19, and inverts the output signal of the voltage comparator when the voltages become the same. For example, the voltage comparator outputs a H-level signal such as a power source potential in an inactive state, and outputs a L-level signal (active state) when the pixel signal and the reference signal agree with each other.
A counter provided posterior to the voltage comparator starts counting operation in synchronization with the transition of the reference signal, either in a down-counting mode or up-counting mode, and stops counting when the output signal of the comparator is inverted and latches (retains and stores) the counted value at that moment as the pixel data, thus completing the AD conversion. Then the AD conversion unit 251 transfers the pixel data to the data storage unit 256 at a predetermined timing, for retaining and storing therein the pixel data.
Thereafter, the column AD circuit 25 sequentially outputs the pixel data in the data storage unit 256 to outside of the column processing unit 26, by shifting operations synchronized with clock signals inputted at a predetermined timing. As a result, picture data (pixel data) is outputted to outside of the chip including the pixel array 10.